The example embodiments of inventive concepts relate to a delay-locked loop (DLL), and more particularly, to a DLL for generating an output clock signal synchronized with a reference clock signal by controlling the phase of the reference clock signal and an electronic device including the same.
A delay line control signal of a DLL using a digital delay line is usually updated while other electronic elements are not performing operations using an output clock signal generated by the DLL. For example, if the number of delay cells performing a delay operation on an input clock signal is changed, the output clock signal may be distorted due to the characteristics of the digital delay line, and consequently the electronic elements using the output clock signal may not operate properly.
Meanwhile, a delay value of the DLL may vary with the change of an external environment while the output clock signal is used by the other electronic elements. If the change of the delay value is compensated for, the electronic elements using the output clock signal can operate more accurately. For example, if the output clock signal of the DLL is used to interface with a memory device like a double data rate (DDR) memory, if the delay change of the DLL due to the change of the external environment is compensated for, the width of a valid data window can be increased, and therefore errors can be reduced during the interfacing.